Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption
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چکیده
Some techniques for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization have shown that we can save power even i f we increase silicon area [7]. In this paper we present a strategy to reduce power consumption in FPGAs based on pipeline architectures working with a low supply voltage.
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تاریخ انتشار 2000